Földesy, Péter and Zarándy, Ákos and Rekeczky, Csaba (2008) Configurable 3D-integrated focal-plane sensor-processor array architecture. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 36 (5-6). pp. 573-588. ISSN 0098-9886
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Abstract
A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources.
| Item Type: | Article |
|---|---|
| Subjects: | T Technology / alkalmazott, műszaki tudományok > TA Engineering (General). Civil engineering (General) / általános mérnöki tudományok T Technology / alkalmazott, műszaki tudományok > TK Electrical engineering. Electronics Nuclear engineering / elektrotechnika, elektronika, atomtechnika |
| SWORD Depositor: | MTMT SWORD |
| Depositing User: | MTMT SWORD |
| Date Deposited: | 12 Sep 2013 12:24 |
| Last Modified: | 12 Sep 2013 12:24 |
| URI: | http://real.mtak.hu/id/eprint/6598 |
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