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The Single-chip Cloud Computer (SCC) is a 48-core experimental processor created by Intel Labs targeting the manycore research community. It has hardware support for sending short messages between cores, while large messages have to go through off-chip shared memory. In this paper we discuss our implementation of the SVP model of concurrency on this architecture, and how we deal with its distributed memory design and communication bottlenecks. We employ our previously developed copy core technique and show which approaches show scalable performance against our original implementation
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