IDPAL - Input Decoupled Partially Adiabatic Logic: Implementation and Examination

Abstract

This thesis presents the experimental results of a four-phase IDPAL eight-input exclusive-OR gate. The following problems with IDPAL are addressed: multistage circuits malfunctioning, simulation convergence anomalies, and inferring input information through the power clock current. EPAD MOSFETs, which provide a low threshold voltage, are shown to be unsuccessful in correcting the malfunctioning behavior of multilayer circuits. A solution to multilayer IDPAL circuits malfunctioning, called IDPAL with discharge, is shown. The differences between simulation waveforms produced by LTspice and the experimental circuits recorded by a Tektronix’s Oscilloscope are investigated. IDPAL is implemented and analyzed using ALD MOSFETs for the following adiabatic families: 2N-2P, IDPAL, and IDPAL with discharge