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oaioai:digitalcommons.usu.edu:ece_facpub-1148

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip

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Publication date
1 September 2014
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Hosted by Utah State University Libraries
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    Abstract

    A fault-tolerant routing algorithm in Network-on-Chip architectures provides adaptivity for on-chip communications. Adding fault-tolerance adaptivity to a routing algorithm increases its design complexity and makes it prone to deadlock and other problem

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    Last time updated on 20/11/2017

    This paper was published in DigitalCommons@USU.

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