Process Variation Aware DRAM (Dynamic Random Access Memory) Design Using Block-Based Adaptive Body Biasing Algorithm

Abstract

Process variation can be defined as the deviation of process parameters from its nominal specifications. Variation is induced by several fundamental effects resulting from inaccuracies in the manufacturing equipment. It is a combination of systematic effects (e.g., lithographic lens aberrations) and random effects (e.g., dopant density fluctuations). The effect of process variation becomes particularly important at smaller process nodes, where the variation accounts for a major percentage of nominal length or width of the device. Process variations translate to a wide range in performance metrics of current designs. As technology scales, these die variations are getting larger, significantly affecting performance and compromising circuit reliability. The variation effect of length, width, and oxide thickness variation on the overall delay values of DRAM circuit is evaluated in this thesis. In this work, a novel method to mitigate the effect of process variation on DRAM circuit is proposed. The timing and leakage parameter which determine the performance of the circuit are sensitive to the base voltage of the transistor. A technique which modifies the base voltage of the transistor to try and mitigate the effect of process variation is used in this work. The circuit is first divided into arbitrary blocks. The base voltage of transistors in these blocks are then modified to achieve nominal timing and leakage values for the DRAM. Simulated annealing-based algorithm is used in order to determine the amount of base voltage required to be applied to each of these blocks