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In the 1980s, when the introduction of public key
cryptography spurred interest in modular multiplication, many
implementations performed modular multiplication using a sum
of residues. As the field matured, sum of residues modular
multiplication lost favor to the extent that all recent surveys
have either overlooked it or incorporated it within a larger class
of reduction algorithms.
In this paper, we present a new taxonomy of modular multiplication
algorithms. We include sum of residues as one of four
classes and argue why it should be considered different to the
other, now more common, algorithms. We then apply techniques
developed for other algorithms to reinvigorate sum of residues
modular multiplication. We compare FPGA implementations of
modular multiplication up to 24 bits wide. The sum of residues
multipliers demonstrate reduced latency at nearly 50% compared
to Montgomery architectures at the cost of nearly doubled circuit
area. The new multipliers are useful for systems based on the
Residue Number System (RNS)
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