Edge effects in silicon IGFETs

Abstract

With the trend for increased miniaturisation in integrated circuits the effect of edges on the d.c. electrical characteristics of insulated gate field effect transistors have become more important. Investigation of these edge effects has been impeded by the lack of suitable test structures. Construction of edge effect test structures requires a microfabrication technique with greater control of relative edge positions than that available with standard microfabrication process. A general technique for that purpose, called the progressional offset technique, was developed during this research. It was applied to the construction of an array of incompletely gated field effect transistors using a custom 1 IL. rn non-self-aligned metal gate enhancement NMOS process. The terms source gap transistors (SGTs), and drain gap transistors (DGTs), were used for the resulting transistors with gaps in gate-tochannel coverage on the source side, and drain side, of the channel. The electrical characteristics of SGTs differ from the normally gated transistors (NGTs) with their increased threshold voltage, increased series resistance, reduced subthreshold performance, and flatter saturation current behaviour. DGTs have a drain-voltage-dependent subthreshold current, and an increased threshold voltage. DGTs with large gaps do not exhibit drain current saturation but have an extended linear region of operation. DGTs are also more sensitive to hot electron degradation. The drain voltage dependent subthreshold swing of DGTs was used to study drain depletion boundary motion and to extract the surface impurity doping concentration. The thesis also contains a comprehensive review of silicon microfabrication techniques, suggestions for other uses of the progressional offset technique, and possible applications for incompletely gated transistors