An FPGA based HSR architecture for seamless PROFINET redundancy

Abstract

This paper presents the mapping of the High-Availability Seamless Redundancy (HSR) protocol to PROFINET RT. Whereas common PROFINET RT components that implement the Media Redundancy Protocol (MRP) are requiring up to 200 ms for recovery after link failures, HSR provides seamless redundancy. In order to overcome the incompatibilities between PROFINET and HSR a configurable HSR RedBox is implemented. The hardware architecture, running at 100 MHz, is mapped onto an Altera Stratix IV FPGA and is capable of processing up to 100 Mbps per port. Using several RedBoxes in a ring, a seamless redundancy is demonstrated for a PROFINET RT test network, using 1 ms cycle time with 3 ms watchdog. The presented architecture is highly configurable and can be mapped both to high-end and low-end FPGAs and therefore fulfills industrial requirements