Repository landing page

We are not able to resolve this OAI Identifier to the repository landing page. If you are the repository manager for this record, please head to the Dashboard and adjust the settings.
oaioai:iris.polito.it:11583/1500007

A programmable BIST architecture for clusters of Multiple-Port SRAMs

Authors
Publication date
1 January 2000
Publisher
place:Washington D.C.
Doi

    Abstract

    This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timin

    Similar works

    Full text

    thumbnail-image

    PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

    redirect
    oaioai:iris.polito.it:11583/15000...
    Last time updated on 30/10/2019

    This paper was published in PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino).

    Having an issue?

    Is data on this page outdated, violates copyrights or anything else? Report the problem now and we will take corresponding actions after reviewing your request.