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Asynchronous implementation techniques, which
measure logic delays at run time and activate registers accordingly,
are inherently more robust than their synchronous
counterparts, which estimate worst-case delays at design time,
and constrain the clock cycle accordingly. De-synchronization is
a new paradigm to automate the design of asynchronous circuits
from synchronous specifications, thus permitting widespread
adoption of asynchronicity, without requiring special design skills
or tools. In this paper, we first of all study different protocols for
de-synchronization and formally prove their correctness, using
techniques originally developed for distributed deployment of
synchronous language specifications. We also provide a taxonomy
of existing protocols for asynchronous latch controllers, covering
in particular the four-phase handshake protocols devised in the
literature for micro-pipelines. We then propose a new controller
which exhibits provably maximal concurrency, and analyze the
performance of desynchronized circuits with respect to the
original synchronous optimized implementation. We finally prove
the feasibility and effectiveness of our approach, by showing
its application to a set of real designs, including a complete
implementation of the DLX microprocessor architecture
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