A memory-based programmable logic device using look-up table cascade with synchronous static random access memories

Abstract

A large-scale memory-technology-based programmable logic device (PLD) using LUT (Look-Up Table) cascade is developed in 0.35um Standard CMOS logic process. Eight 64K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) flexible cascade connection structure, 2) multi-phase pseudo-asynchronous operations with synchronous SRAM cores, 3) LUT-bypass redundancy. This chip operates at 33MHz in 8-LUT cascades with 122mW. Benchmark results show that it achieves a comparable performance to FPGAs