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oaioai:ojs.journal.utem.edu.my:article/1749

A Novel Parallel Hardware Architecture for Inter Motion Estimation in HEVC

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Publication date
15 March 2017
Publisher
Journal of Telecommunication, Electronic and Computer Engineering (JTEC)

Abstract

High Efficiency Video Coding (HEVC) standard, generated by ITU, can provide compression ratio twice more than current H.264/ MPEG-4. To date, only a few hardware have been implementated for Integer Motion Estimation (IME) to date. In this paper, a parallel hardware architecture for IME in HEVC encoder is proposed. This design uses Rot-WDiamond (RWD) algorithm to reduce computational load and parallelism to improve processing speed. Therefore, this design can reach 4K (4096×2160) video in real time at 60 frames per second (fps) and achieve the frequency of 125MHz

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Universiti Teknikal Malaysia Melaka: UTeM Open Journal System

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Last time updated on 17/10/2019

This paper was published in Universiti Teknikal Malaysia Melaka: UTeM Open Journal System.

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