Reconfigurable Logic Embedded Architecture of Support Vector Machine Linear Kernel

Abstract

Support Vector  Machine  (SVM) is a linear  binary classifier  that  requires a  kernel  function  to  handle  non-linear problems.  Most  previous  SVM  implementations for  embedded systems  in literature were  built  targeting a certain  application; where analyses were done through comparison  with software im- plementations only. The impact  of different  application datasets towards  SVM hardware performance were not analyzed.  In this work,  we propose  a parameterizable linear  kernel  architecture that  is fully pipelined.  It  is prototyped and  analyzed  on Altera Cyclone  IV  platform   and  results  are  verified  with  equivalent software  model.  Further analysis  is  done  on  determining the effect  of  the  number of  features   and  support   vectors  on  the performance of the  hardware architecture. From  our  proposed linear  kernel  implementation, the number of features  determine the maximum  operating frequency  and amount  of logic resource utilization,  whereas  the  number of support   vectors  determines the  amount  of on-chip  memory  usage  and  also the  throughput of the system