Design of Low Power, High Speed Frequency Multiplier Based On DPLL for Clock Generation

Abstract

A low-power and high-speed frequency multiplier for a DPLL-based clock generator is proposed to produce a multiplied clock with a high frequency and a greatest frequency rang. The proposed frequency multiplier devours low power and accomplishes a rapid activity. The proposed frequency multiplier minimizes the delay difference between the positive and negative edge generation paths. This is fabricated in a 0.12μm CMOS process technology and accomplished power utilization to a frequency ratio of 0.698mw, and it generates 59 phase differential clocksand has the maximum multiplication ratio of 33, and an output range of 100MHz