Low Power FinFET based SRAM Cell Design

Abstract

With the incessant developments occurring in VLSI circuits and systems arena and power dissipation becoming a major design constraint, the power component can be considerably reduced through efficient designing of the SRAM memory elements. Nowadays, multi-gate devices such as the FinFETs play a prominent role in reducing the power dissipation that what was found realizable by the conventional CMOS devices. Additionally, the FinFETs are found to be capable of overcoming some of the major drawbacks of the conventional CMOS devices, namely, the leakage current, the sub-threshold leakage, parasitic capacitance etc. This paper uses 32nm FinFET devices for the implementation of the 6T, 7T SRAM cell architectures and the resultant power is calculated for the read and write operations, to study the comparative benefits of the use of FinFETs in the memory cells than that of the CMOS counterpart circuits. Industry standard Cadence EDA tools have been employed for the simulations. The layout designs of 6T and 7T SRAM cells have been carried out using 180nm CMOS technology library for post layout simulations