A Review on Design and Development of Pipelined Quaternary Adder for Fast Addition

Abstract

Design of the binary logic circuits is limited by the requirement of the interconnections. A possible solution could be arrived at by using a larger set of signals over the same chip area. Multiple-valued logic (MVL) designs are gaining importance from that perspective. This paper presents the design of a multiple-valued half adder and full adder circuits. In Quaternary adders the binary value is first converted into the Quaternary value and then the addition operation is performed with less number of gates and minimum depth of net. Sum and carry are processed in two separate blocks, controlled by code generator unit. Simple pass transistors are used for implementation. Area of the designed circuits is less than the corresponding binary circuits and quaternary adders because number of transistors used are less. We can implement this paper by using pipelining which help us to reduce the delay of operation and also help us to improve the throughput of the system, the designing of the paper is done by using VHDL. DOI: 10.17762/ijritcc2321-8169.15034