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'Institute of Electrical and Electronics Engineers (IEEE)'
Abstract
Nano-crossbar arrays have emerged as area and power efficient
structures with an aim of achieving high performance computing
beyond the limits of current CMOS. Due to the stochastic nature
of nano-fabrication, nano arrays show different properties both
in structural and physical device levels compared to conventional
technologies. Mentioned factors introduce random characteristics
that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic
technology preference for switching elements, defect or fault rates
of the given nano switching array and the variation values as well
as their effects on performance metrics including power, delay, and
area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization
algorithms for each step of the process.This work is part of a project that has received funding from the
European Union’s H2020 research and innovation programme under the
Marie Skłodowska-Curie grant agreement No 691178, and supported by the
TUBITAK-Career project #113E76
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