Physics-based compact model for IIIV digital logic FETs including gate tunneling leakage and parasitic capacitance

Abstract

A physics-based compact model is developed for IIIV field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the IIIV compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects. �� 2011 IEEE.Manuscript received May 13, 2010; revised September 30, 2010 and December 4, 2010; accepted January 2, 2011. Date of current version March 23, 2011. This work was supported in part by the National Science Foundation under Grant ECS 0501096, by the Focus Center Research Program (Materials, Structures, and Devices and Center for Circuits and Systems Solutions), and by Intel Corporation. The work of S. Oh was supported in part by Samsung Scholarship and The Burt and Deedee McMurtry Stanford Graduate Fellowship Fund. The review of this paper was arranged by Editor S. Bandyopadhyay