A Performance evaluation of several ATM switching architectures

Abstract

The goal of this thesis is to evaluate the performance of three Asynchronous Transfer Mode switching architectures. After examining many different ATM switching architectures in literature, the three architectures chosen for study were the Knockout switch, the Sunshine switch, and the Helical switch. A discrete-time, event driven system simulator, named ProModel, was used to model the switching behavior of these architectures. Each switching architecture was modeled and studied under at least two design configurations. The performance of the three architectures was then investigated under three different traffic types representative of traffic found in B-ISDN: random, constant bit rate, and bursty. Several key performance parameters were measured and compared between the architectures. This thesis also explored the implementation complexities and fault tolerance of the three selected architectures