Switched-Capacitor Voltage Doubler Design Using 0.5 μm Technology

Abstract

While integrated circuit (IC) power management has been an eternal topic for chip designers, inductor based DC-DC converters have been dominant in the field for years. However, because of the natures of inductors: large electro-magnetic interference, high coupling noise, and difficult silicon fabrication process, they are not favorable to on-chip solutions. Switched-capacitor (SC) DC-DC converters, which adopt capacitors for their energy storage components, have become increasingly popular among both the academia and the industry, because, apparently, they avoid the drawbacks of the inductor counterparts, and can be directly implemented on-chip without additional fabrication process. In this paper, we will investigate one of the most famous SC voltage doubler topologies, which is known as Favrat Cell . By designing a chip, which converts 1.5 V voltage input to 2.5 V voltage output at 1 mA current load, we will walk through the details of a SC DC-DC converter design, including the switch cell, timing system, regulation loop and efficiency analysis. The design uses two 200 pF pumping capacitors and a 400 pF output capacitor in On-Semi half-micron technology. Four-way interleaved phase structure is adopted to reduce the output voltage ripple. The gate-drive strategy of the switches has been improved to further reduce the reverse current injections during transitions. A new high-ratio voltage booster topology based on the cross-coupled topology has been introduced and will be discussed in comparison with the Dickson charge pump topology