Repository landing page

We are not able to resolve this OAI Identifier to the repository landing page. If you are the repository manager for this record, please head to the Dashboard and adjust the settings.
oaioai:ro.ecu.edu.au:theses-1027

A jittered-sampling correction technique for ADCs

Authors
Publication date
1 January 2008
Publisher
Edith Cowan University, Research Online, Perth, Western Australia
Doi

    Abstract

    In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied

    Similar works

    Full text

    thumbnail-image

    This paper was published in Research Online @ ECU.

    Having an issue?

    Is data on this page outdated, violates copyrights or anything else? Report the problem now and we will take corresponding actions after reviewing your request.