Design of a Mips Instruction Set Simulator for Multicore Processor Research in Systemc

Abstract

The main focus of this thesis is to design a MIPS Instruction Set Simulator (ISS) for multicore computer architecture research. This MIPS ISS is tested thoroughly for each instruction and by long test benches. Usual ISS works in a purely functional way unlike real hardware, this ISS is designed at a level more abstract than RTL but closer to real processor which will be easy to interface with other cores, caches and micro-architectural parts.School of Electrical & Computer Engineerin