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PhD ThesisAs silicon cost reduces, the demands for higher performance and lower power consumption
are ever increasing. The ability to dynamically control the number of resources
employed can help balance and optimise a system in terms of its throughput, power
consumption, and resilience to errors. The management of multiple resources requires
building more advanced resource allocation logic than traditional 1-of-N arbiters posing
the need for the efficient design flow supporting both the design and verification of such
systems.
Networks-on-Chip provide a good application example of distributed arbitration, in
which the processor cores needing to transmit data are the clients; and the point-to-point
links are the resources managed by routers. Building fast and smart arbiters can greatly
benefit such systems in providing efficient and reliable communication service.
In this thesis, a multi-resource arbiter was developed based on the Signal Transition
Graph (STG) development flow. The arbiter distributes multiple active interchangeable
resources that initiate requests when they are ready to be used. It supports concurrent
resource utilization, which benefits creating asynchronous Multiple-Input-Multiple-
Output (MIMO) queues.
In order to deal with designs of higher complexity, an arbiter-oriented design flow is
proposed. The flow is based on digital circuit components that are represented internally
as STGs. This allows designing circuits without directly working with STGs but allowing
their use for synthesis and formal verification. The interfaces for modelling, simulation,
and visual model representation of the flow were implemented based on the existing
modelling framework. As a result, the verification phase of the flow has helped to find
hazards in existing Priority arbiter implementations.
Finally, based on the logic-gate flow, the structure of a low-latency general purpose
arbiter was developed. This design supports a wide variety of arbitration problems including
the multi-resource management, which can benefit building NoCs employing
complex and adaptive routing techniques.EPSRC grant GR/E044662/1 (STEP
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