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Modulo scheduling for a fully-distributed clustered VLIW architecture
Abstract
Clustering is an approach that many microprocessors are adopting in recent times in order to mitigate the increasing penalties of wire delays. We propose a novel clustered VLIW architecture which has all its resources partitioned among clusters, including the cache memory. A modulo scheduling scheme for this architecture is also proposed. This algorithm takes into account both register and memory inter-cluster communications so that the final schedule results in a cluster assignment that favors cluster locality in cache references and register accesses. It has been evaluated for both 2- and 4-cluster configurations and for differing numbers and latencies of inter-cluster buses. The proposed algorithm produces schedules with very low communication requirements and outperforms previous cluster-oriented schedulers.Peer ReviewedPostprint (published version- Conference report
- Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
- Parallel processing (Electronic computers)
- Cache memory
- Microprocessors
- VLIW
- Processor scheduling
- Delay
- Clustering algorithms
- Scheduling algorithm
- Registers
- Wire
- Cache memory
- Partitioning algorithms
- Processament en paral·lel (Ordinadors)
- Memòria cau
- Microprocessadors