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Hardware-software co-design of an iris recognition algorithm
Abstract
This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.Peer ReviewedPreprin- Article
- Àrees temàtiques de la UPC::Informàtica::Programació
- Àrees temàtiques de la UPC::Ciències de la visió::Optometria
- Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
- Àrees temàtiques de la UPC::Ciències de la salut::Medicina::Oftalmologia
- Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal::Reconeixement de formes
- Iris (Eye)
- Microprocessors--Programming
- Algorithms and architectures for advanced scientific computing
- Computer software--Development
- Algorismes computacionals -- Processament de dades
- Disseny SOC
- Iris (Ull)
- Microprocessadors -- Disseny -- Informàtica