We are not able to resolve this OAI Identifier to the repository landing page. If you are the repository manager for this record, please head to the Dashboard and adjust the settings.
The development of modern ICs requires a huge investment in RTL verification.
This is a reflection of brisk release schedules and the complexity of
contemporary chip designs. A major bottleneck to reaching verification closure
in such designs is the disproportionate effort expended in crafting directed
tests; which is necessary to reach those behaviors that other, more automated
testing methods fail to cover. This paper defines a novel language that can be
used to generate targeted stimuli for RTL logic and which mitigates the
complexities of writing directed tests. The main idea is to treat directed
testing as a meta-reasoning problem about simulation. Our language is both
formalized and prototyped as a proof-search strategy language in rewriting
logic. We illustrate its novel features and practical use with several
examples.published or submitted for publicatio
Is data on this page outdated, violates copyrights or anything else? Report the problem now and we will take corresponding actions after reviewing your request.