Recent Trends and Considerations for High Speed Data in Chips and System Interconnects

Abstract

This paper discusses key issues related to the design of large processing volume chip architectures and high speed system interconnects. Design methodologies and techniques are discussed, where recent trends and considerations are highlighted.Grant number : This work was supported by the Spanish Ministry of Economy and Competitiveness project NANOWAVE (PIB2010BZ-00585). Part of this work has been supported by the Generalitat de Catalunya under grant 2014 SGR1551.© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works